Editorial update: 11 October 2026. A reproduced trade-publication article has been replaced with an independent worked explanation. Examples below are illustrative, not measurements of a particular 7 nm or 5 nm process.

A smaller fabrication-node label does not tell a designer how much energy a completed task will use. Workload, supply voltage, switching activity, leakage, memory traffic and execution time all matter. The question is whether the full system does the required work reliably within its energy budget.

A useful first approximation

Texas Instruments' CMOS power application report distinguishes static and dynamic consumption and explains the contribution of frequency, capacitance and voltage. A common switching-power approximation is P = α × C × V² × f, where α describes switching activity. This is an introductory model; it does not replace the characterised libraries and tools for an advanced process.

Work through the arithmetic

Assume a hypothetical block uses 1 watt of switching power at 1.0 volt. Holding activity, capacitance and frequency constant, changing the supply to 0.8 volt gives a modelled switching power of 0.64 watt: (0.8 / 1.0)² = 0.64. That is a 36% reduction in this component, not a guaranteed 36% reduction in total device energy.

Now suppose the lower-voltage implementation takes twice as long to complete the task. Even before counting leakage, 0.64 watt for two seconds uses 1.28 joules, compared with 1 joule for the original one-second run. This constructed example shows why comparing watts alone can reverse the conclusion.

Leave room for variation

Design evaluation should cover the specified operating conditions, not just one nominal simulation. Record the voltage and temperature range, the timing target, the workload, and the process models supplied for the technology. A power saving that produces timing failures is not a usable operating point.

Measurement	Question answered
Peak power	Can the supply and thermal system handle the demand?
Energy per completed task	Does the change reduce the cost of useful work?
Idle consumption	What is spent while waiting?
Timing and error checks	Does the workload still complete correctly?

Use the same task, accuracy target and reporting boundary when comparing designs. State whether memory and peripherals are included. Otherwise a gain inside the compute block may simply move consumption somewhere else.

Compare energy per completed task, including idle time

For a hypothetical chip running a task, reducing power from 2 watts to 1 watt is not necessarily an energy saving if execution time rises from one second to three. The first case uses 2 joules and the second 3 joules within that simplified boundary. These are illustrative numbers, not measurements of a fabrication process.

Include memory traffic, idle time and the required correctness or timing when choosing the comparison. A lower voltage or smaller node label is one design fact, not the final outcome. Report useful work per energy under the specified conditions so the efficiency claim remains connected to the task.